一、概述一个主芯片FPGA把来自两个外设cameraIMU的数据通过hololink逻辑模块整合下打包通过光口传出NVIDIA Hololink IP 的顶层 SystemVerilog 模块属于传感器→主机之间的高速图像 / 数据传输处理核心是一个高度参数化、可配置、多时钟域、带协议处理的完整 FPGA 以太网 传感器桥接 SoC。主要应用在工业/医疗/车载图像传感器数据上云二、HOLOLINK 逻辑视图HOLOLINK 顶层模块把五大系统子模块的信息进行整合并输出其核心功能模块可划分为时钟复位管理子系统、主机接口HIF子系统、传感器接口SIF子系统、PTP 时间同步子系统、控制与外设子系统它们都是通过统一 AXI-Stream互连以及APB配置1、时钟复位管理子系统该子系统包含多时钟域HIF、APB、PTP、SIF_RX、SIF_TX异步复位生成reset_gen IP核reset_gen #( .NUM_SENSOR_RX ( NUM_SENSOR_RX ), .NUM_SENSOR_TX ( NUM_SENSOR_TX ) ) u_rst_gen( .i_sys_rst ( i_sys_rst ), .i_cfg_rst ( o_sw_sys_rst ), .i_sif_rx_clk ( sif_rx_clk ), .i_sif_tx_clk ( sif_tx_clk ), .i_hif_clk ( i_hif_clk ), .i_apb_clk ( i_apb_clk ), .i_ptp_clk ( i_ptp_clk ), .o_sif_rx_rst ( sif_rx_rst ), .o_sif_tx_rst ( sif_tx_rst ), .o_hif_rst ( o_hif_rst ), .o_apb_rst ( o_apb_rst ), .o_ptp_rst ( o_ptp_rst ) );也包含跨时钟域同步的data_sync、streaming_cdc IP 核PTP 时间 → 同步到 主机时钟域 (HIF)以及PTP 时间 → 同步到 APB 配置时钟域可消除亚稳态、毛刺、不定态、偶尔翻车data_sync u_eeprom_ip_addr_vld_sync ( .clk ( i_hif_clk ), // 目标时钟HIF主机时钟域 .rst_n ( !o_hif_rst ), // 目标时钟域复位 .sync_in ( eeprom_ip_addr_vld ), // 源APB时钟域来的有效标志1bit .sync_out ( eeprom_ip_addr_vld_hif_clk ) // 输出同步到 HIF 时钟域 ); streaming_cdc #( .DATA_WIDTH ( 80 ), .SRC_FREQ ( PTP_CLK_FREQ ), .DST_FREQ ( HIF_CLK_FREQ ) ) u_ptp_hif_cdc ( .i_src_clk ( i_ptp_clk ), .i_dst_clk ( i_hif_clk ), .i_src_rst ( o_ptp_rst ), .i_dst_rst ( o_hif_rst ), .i_src_data ( {ptp_sec, ptp_nano_sec} ), .o_dst_data ( {ptp_sec_sync_hif, ptp_nano_sec_sync_hif} ), .o_dst_valid ( ptp_sync_hif_valid ) ); streaming_cdc #( .DATA_WIDTH ( 80 ), .SRC_FREQ ( PTP_CLK_FREQ ), .DST_FREQ ( APB_CLK_FREQ ) ) u_ptp_apb_cdc ( .i_src_clk ( i_ptp_clk ), .i_dst_clk ( i_apb_clk ), .i_src_rst ( o_ptp_rst ), .i_dst_rst ( o_apb_rst ), .i_src_data ( {ptp_sec, ptp_nano_sec} ), .o_dst_data ( {ptp_sec_sync_apb, ptp_nano_sec_sync_apb} ), .o_dst_valid ( ptp_sync_apb_valid ) );2、主机接口HIF子系统该子系统包含以太网帧解析、协议解封装ETH/IP/UDP/PTPrx_parser IP核generate for (i0; iHOST_IF_INST; i) begin: gen_rx_parser assign o_hif_axis_tready [i] init_done_hif_clk; rx_parser #( .AXI_DWIDTH ( HOST_WIDTH ), .AXI_LS_DWIDTH ( 8 ), .MTU ( HOST_MTU ), .NUM_LS_INST ( NUM_LS_RX_INST ), .SYNC_CLK ( SYNC_CLK_HIF_APB ) ) rx_parser ( .host_clk ( i_hif_clk ), .host_rst ( o_hif_rst ), .apb_clk ( i_apb_clk ), .apb_rst ( o_apb_rst ), //Configuration .i_dev_mac_addr ( dev_mac_addr [i] ), .i_dev_ip_addr ( dev_ip_addr [i] ), //Register APB Interfaces .i_apb_m2s ( s_apb_m2s_host [(i*num_host_mod)inst_dec] ), .o_apb_s2m ( s_apb_s2m_host [(i*num_host_mod)inst_dec] ), .o_dest_info ( dest_info [i] ), .o_ptp_sync_msg ( is_ptp_sync_msg [i] ), //AXI RX Interface inbound from packet buffer (via Ethernet MAC) .i_axis_rx_tvalid ( i_hif_axis_tvalid [i] init_done_hif_clk ), .i_axis_rx_tdata ( i_hif_axis_tdata [i] ), .i_axis_rx_tlast ( i_hif_axis_tlast [i] ), .i_axis_rx_tuser ( i_hif_axis_tuser [i] ), .i_axis_rx_tkeep ( i_hif_axis_tkeep [i] ), // Sensor TX Interface .o_stx_axis_tvalid ( stx_axis_tvalid [i] ), .o_stx_axis_tdata ( stx_axis_tdata [i] ), .o_stx_axis_tlast ( stx_axis_tlast [i] ), .o_stx_axis_tuser ( stx_axis_tuser [i] ), .o_stx_axis_tkeep ( stx_axis_tkeep [i] ), // PTP Interface .o_ptp_axis_tvalid ( ptp_rx_axis_tvalid [i] ), .o_ptp_axis_tdata ( ptp_rx_axis_tdata [i] ), .o_ptp_axis_tlast ( ptp_rx_axis_tlast [i] ), .o_ptp_axis_tuser ( ptp_rx_axis_tuser [i] ), .o_ptp_axis_tkeep ( ptp_rx_axis_tkeep [i] ), //Bridge TX AXIS Interface .o_btx_axis_tvalid ( brx_axis_tvalid [i] ), .o_btx_axis_tdata ( brx_axis_tdata [i] ), .o_btx_axis_tlast ( brx_axis_tlast [i] ), .o_btx_axis_tuser ( brx_axis_tuser [i] ), .o_btx_axis_tkeep ( brx_axis_tkeep [i] ), .i_btx_axis_tready ( brx_axis_tready [i] ), //Low Speed AXIS Interface to datapath .o_ls_axis_tvalid ( lsi_axis_tvalid [i] ), .o_ls_axis_tdata ( lsi_axis_tdata [i] ), .o_ls_axis_tlast ( lsi_axis_tlast [i] ), .o_ls_axis_tuser ( lsi_axis_tuser [i] ), .o_ls_axis_tkeep ( lsi_axis_tkeep [i] ), .i_ls_axis_tready ( lsi_axis_tready [i] ) ); assign s_apb_s2m_host [(i*num_host_mod)ctrl_evt].pready 0; assign s_apb_s2m_host [(i*num_host_mod)ctrl_evt].prdata 0; assign s_apb_s2m_host [(i*num_host_mod)ctrl_evt].pserr 0; end endgenerate包含具有低速控制帧解析、IP/MAC 管理、事件上报功能的rx_ls_parser IP 核rx_ls_parser #( .AXI_DWIDTH ( HOST_WIDTH ), .AXI_LS_DWIDTH ( 8 ), .ENUM_DWIDTH ( ENUM_DWIDTH ), .MTU ( HOST_MTU ), .NUM_LS_RX_INST ( NUM_LS_RX_INST ), .NUM_LS_TX_INST ( NUM_LS_TX_INST ), .NUM_HOST ( HOST_IF_INST ), .UUID ( UUID ), .SYNC_CLK ( SYNC_CLK_HIF_APB ) ) u_rx_ls_parser ( .i_pclk ( i_hif_clk ), .i_prst ( o_hif_rst ), .i_aclk ( i_apb_clk ), .i_arst ( o_apb_rst ), .i_apb_m2s_ecb ( s_apb_m2s_dev [3] ), .o_apb_s2m_ecb ( s_apb_s2m_dev [3] ), .i_apb_m2s_evt ( s_apb_m2s_dev [2] ), .o_apb_s2m_evt ( s_apb_s2m_dev [2] ), .o_apb_m2s_evt ( m_apb_m2s [3] ), .i_apb_s2m_evt ( m_apb_s2m [3] ), .i_apb_m2s_ram ( s_apb_m2s_ram [1] ), .o_apb_s2m_ram ( s_apb_s2m_ram [1] ), //Low Speed AXIS Interface to Packet proc .i_axis_tvalid ( lsi_axis_tvalid ), .i_axis_tdata ( lsi_axis_tdata ), .i_axis_tlast ( lsi_axis_tlast ), .i_axis_tuser ( lsi_axis_tuser ), .i_axis_tkeep ( lsi_axis_tkeep ), .o_axis_tready ( lsi_axis_tready ), // Input Control Data .i_init_done ( init_done_hif_clk ), .i_ptp_clk ( i_ptp_clk ), .i_ptp_rst ( o_ptp_rst ), .i_ptp ( {ptp_sec, ptp_nano_sec} ), .i_ptp_hif ( {ptp_sec_sync_hif, ptp_nano_sec_sync_hif} ), .i_dev_mac_addr ( dev_mac_addr ), .i_eeprom_ip_addr ( eeprom_base_ip_addr ), .i_eeprom_ip_addr_vld ( eeprom_ip_addr_vld_hif_clk ), .i_hsb_stat ( hsb_stat ), .o_dev_ip_addr ( dev_ip_addr ), .i_enum_data ( enum_data ), .i_evt_vec ( event_vec ), .i_pkt_inc ( pkt_inc ), .i_pps ( pps ), // APB interface .o_apb_m2s_ecb ( m_apb_m2s [0] ), .i_apb_s2m_ecb ( m_apb_s2m [0] ), //Low Speed AXIS Interface to ethernet output at full speed .o_axis_tvalid ( lso_axis_tvalid ), .o_axis_tdata ( lso_axis_tdata ), .o_axis_tlast ( lso_axis_tlast ), .o_axis_tuser ( lso_axis_tuser ), .o_axis_tkeep ( lso_axis_tkeep ), .i_axis_tready ( lso_axis_tready ) );包含具有发送端优先级调度数据面 PTP 控制 流控 桥接的IP 核generate for (i0; iHOST_IF_INST; i) begin: gen_eth_pkt assign tx_axis_tvalid[i] {btx_axis_tvalid [i], // bridge pause_axis_tvalid [i], // pause lso_axis_tvalid [i], // arp/icmp/udp_loopback ptp_tx_axis_tvalid_gated [i], // ptp dp_axis_tvalid [i]}; // sensor data assign tx_axis_tlast[i] {btx_axis_tlast [i], pause_axis_tlast [i], lso_axis_tlast , ptp_tx_axis_tlast [i], dp_axis_tlast [i]}; assign tx_axis_tdata[i] { dp_axis_tdata [i], ptp_tx_axis_tdata [i], lso_axis_tdata , pause_axis_tdata [i], btx_axis_tdata [i]}; assign tx_axis_tkeep[i] { dp_axis_tkeep [i], ptp_tx_axis_tkeep [i], lso_axis_tkeep , pause_axis_tkeep [i], btx_axis_tkeep [i]}; assign tx_axis_tuser[i] { btx_axis_tuser [i], pause_axis_tuser [i], lso_axis_tuser , ptp_tx_axis_tuser [i], dp_axis_tuser [i]}; assign {btx_axis_tready [i], pause_axis_tready [i], lso_axis_tready [i], ptp_tx_axis_tready [i], dp_axis_tready [i]} tx_axis_tready[i]; eth_pkt #( .N_INPT ( PORT_NUM ), .W_DATA ( HOST_WIDTH ), .SYNC_CLK ( SYNC_CLK_HIF_APB ) ) u_eth_pkt ( .i_pclk ( i_hif_clk ), .i_prst ( o_hif_rst ), // Register Map, abp clk domain .i_aclk ( i_apb_clk ), .i_arst ( o_apb_rst ), .i_apb_m2s ( s_apb_m2s_host [(i*num_host_mod)eth_pkt] ), .o_apb_s2m ( s_apb_s2m_host [(i*num_host_mod)eth_pkt] ), .o_pkt_inc ( pkt_inc [i] ), //PTP Timestamp .o_ptp_val ( ptp_val [i] ), .o_del_req_val ( del_req_val [i] ), // AXIS From Multiple Sources .i_axis_tvalid ( tx_axis_tvalid [i] ), .i_axis_tlast ( tx_axis_tlast [i] ), .i_axis_tkeep ( tx_axis_tkeep [i] ), .i_axis_tdata ( tx_axis_tdata [i] ), .i_axis_tuser ( tx_axis_tuser [i] ), .o_axis_tready ( tx_axis_tready [i] ), // AXIS to MAC .o_axis_tvalid ( o_hif_axis_tvalid [i] ), .o_axis_tlast ( o_hif_axis_tlast [i] ), .o_axis_tdata ( o_hif_axis_tdata [i] ), .o_axis_tkeep ( o_hif_axis_tkeep [i] ), .o_axis_tuser ( o_hif_axis_tuser [i] ), .i_axis_tready ( i_hif_axis_tready [i] ) ); end endgenerate3、传感器接口SIF子系统packetizer_top传感器数据分片、虚拟端口VP打包dp_pkt_top数据面封装ETHIPUDP 头、PTP 时间戳插入sensor_tx_pkt_proc控制帧转发到传感器tx_stream_buffer传感器输出流控与缓冲4、PTP 时间同步子系统ptp_topIEEE 1588-2008 PTPv2 协议栈输出秒 / 纳秒 / 1PPS跨时钟域同步到 HIF/APB5、控制与外设子系统apb_intc_topAPB 总线中央路由sys_init eeprom_info上电初始化、MAC / 序列号读取glb_ctrl_top全局寄存器、GPIO、软件复位SPI/I2C/UART外设控制器桥接BRIDGEFPGA-FPGA 数据转发、路由表6、模块间关系逻辑接口所有模块通过AXI-Stream互联tvalid/tlast/tdata/tkeep/tuser所有配置通过APB总线完成时钟复位由reset_gen统一分发三、总结上面总结一句话就是告知系统要做什么、由哪些功能模块组成、以及模块间接口关系。由于代码与内容篇幅比较长后面三部分做简单的总结全部代码可加vx hope_0793一起讨论咨询