Sim/circuit1This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.观察可以发现这就是一个与门。代码如下module top_module ( input a, input b, output q );// assign q a b; // Fix me endmoduleSim/circuit2This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.看这个waveform看q第一个高电平a,b,c,d全是1第二个高电平a,b低电平c,d高电平第三个高电平a,c --0,b,d---1;a,d---0,b,c---1;a,d--1,好的咱们已经发现规律了原来这是一个同或电路也就是0个或者2个或者4个为1的时候输出q为1代码如下module top_module ( input a, input b, input c, input d, output q );// assign q ~a^b^c^d; // Fix me endmoduleSim/circuit3由于上一题的经验我想直接猜抑或但是不然于是观察waveform发现 bc bd ad ac的时候q1那么代码如下module top_module ( input a, input b, input c, input d, output q );// assign q ad | ac |bc |bd; // Fix me endmoduleSim/circuit4一看就是bc代码如下module top_module ( input a, input b, input c, input d, output q );// assign q b|c; // Fix me endmoduleSim/circuit5c是选择信号selsel0c0选择b这样子代码如下module top_module ( input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, input [3:0] e, output [3:0] q ); always (*) begin case (c) 4h0: q b; 4h1: q e; 4h2: q a; 4h3: q d; default: q 4hf; // Covers c 4 through F endcase end endmoduleSim/circuit6我们直接看这个电路也是感觉和上一道题一样a来选择q代码如下module top_module ( input [2:0] a, output [15:0] q ); always (*)begin case(a) 3d0: q 16h1232; 3d1: q 16haee0; 3d2: q 16h27d4; 3d3: q 16h5a0e; 3d4: q 16h2066; 3d5: q 16h64ce; 3d6: q 16hc526; 3d7: q 16h2f19; endcase end endmoduleSim/circuit7这个clk开始a上升沿q变成0代码如下module top_module ( input clk, input a, output q ); always(posedge clk)begin q 1; if(a)begin q 0; end end endmoduleSim/circuit8First we could see p, when clk and a is true, the p is set tobe true.q只在clock的下降沿发生变化代码如下module top_module ( input clock, input a, output reg p, output reg q ); // 逻辑 p高电平透明锁存器 (High-level sensitive latch) // 规律clock 为高时p 实时跟随 a 的变化clock 为低时p 保持之前的值。 always (*) begin if (clock) begin p a; end // 注意此处不写 else会自动产生锁存行为符合波形图 t120 后的保持特征 end // 逻辑 q下降沿触发器 (Negative-edge triggered flip-flop) // 规律q 只在 clock 的下降沿1变0的瞬间改变采样此时 p 的值。 always (negedge clock) begin q p; end endmoduleSim/circuit9这个感觉像是计数器每当a的下降沿的下一个clock开始从4开始计数代码如下module top_module ( input clk, input a, output [3:0] q ); always (posedge clk)begin if(a)begin q 4d4; end else if ( q 6 ) begin q 4d0; end else begin q q 1d1; end end endmoduleSim/circuit10直接懵了啊看不出有啥规律我只知道组合和逻辑都有代码如下参考https://blog.csdn.net/qq_24999747/article/details/124708510module top_module ( input clk, input a, input b, output q, output state ); always(posedge clk)begin if(ab) state 1b1; else if(!(a||b)) state 1b0; else state state; end assign q state?(a~^b):(a^b); endmodule